void LPSPI0_Init_Master(void) { /* disable the LPSPI0 clock(clear first,then set parameters such as PCS etc) */ DISABLE_PORT_CLOCK(PCC_LPSPI0_INDEX); /* PCC LPSPI0 Register configuration: * Field Descriptions * [31] PR 1b - Peripheral is present. * [30] CGC 1b - Clock enabled.Lock the clock selection.(can't change) * [26:24] PCS 110b - clock option 6(SPLLDIV2_CLK:40MHz) */ PCC->PCCn[PCC_LPSPI0_INDEX] |= PCC_PCCn_PR(0b1) | PCC_PCCn_CGC(0b1) | PCC_PCCn_PCS(0b110); /* Disable LPSPI0 Module Configuration: * Field Descriptions * [9] RRF 0b - Receive FIFO not reset * [8] RTF 0b - Transmit FIFO not reset * [3] DBGEN 0b - LPSPI module is disabled in debug mode * [2] DOZEN 0b - LPSPI module is enabled in Doze mode * [1] RST 0b - Module is not reset * [0] MEN 0b - Module is disabled */ LPSPI0->CR = 0x00000000; /* Interrupt : * Field Descriptions * [1] RDIE 1b - Receive Data Interrupt Enable * */ LPSPI0->IER |= LPSPI_IER_RDIE_MASK; /* DMA request is disabled */ LPSPI0->DER = 0x00000000; /* Configuration Register 0 setup: * Field Descriptions * [9] RDMO 0b - Received data is stored in the receive FIFO as in normal operations * [8] CIRFIFO 0b - Circular FIFO is disabled * [0] HREN 0b - Host request is disabled * */ LPSPI0->CFGR0 = 0x00000000; /* Configuration Register 1 setup: * Field Descriptions * [27] PCSCFG 0b - PCS[3:2] are enabled * [26] OUTCFG 0b - Output data retains last value(not tri-state) when CS is negated * [25:24] PINCFG 00b - SIN is used for input data and SOUT is used for output data * [18:16] MATCFG 000b - Match is disabled * [11:8] PCSPOL 0000b - PCSx is active low * [3] NOSTALL 1b - Transfers will not stall when the transmit FIFO is empty or the receive FIFO is full * [2] AUTOPCS 0b - Automatic PCS generation is disabled * [1] SAMPLE 0b - Input data is sampled on SCK edge * [0] MASTER 1b - Master Mode */ LPSPI0->CFGR1 |= LPSPI_CFGR1_NOSTALL(0b1) | LPSPI_CFGR1_MASTER(0b1); /* Transmit Command Register Configuration(only be written using 32-bit writes): * Field Description * [31] CPOL 0b - The inactive state value of SCK is low * [30] CPHA 1b - Data is changed on the leading edge of SCK and captured on the following edge of SCK * [29:27] Prescale 010b - Functional clock devided by 2^2 = 4 * [25:24] PCS 00b - Transfer using LPSPI_PCS[0] * [23] LSBF 0b - MSB first * [22] BYSW 0b - Byte Swap is disabled * [21] CONT 0b - Continuous transfer is enabled * [20] CONTC 0b - Command word for start of new transfer * [19] RXMSK 0b - Normal transfer * [18] TXMSK 0b - Normal transfer * [17:16] WIDTH 00b - 1-bit transfer * [11:0] FRAMESZ 000000000111b - the frame size equals to 7+1 = 8 bits */ LPSPI0->TCR = (LPSPI_TCR_CPOL(0b0) | LPSPI_TCR_CPHA(0b1) | LPSPI_TCR_PRESCALE(0b010) | LPSPI_TCR_PCS(0b00) | LPSPI_TCR_LSBF(0b0) | LPSPI_TCR_BYSW(0b0) | LPSPI_TCR_CONT(0b1) | LPSPI_TCR_CONTC(0b0) | LPSPI_TCR_RXMSK(0b0) | LPSPI_TCR_TXMSK(0b0) | LPSPI_TCR_WIDTH(0b00) | LPSPI_TCR_FRAMESZ(7)); /* Clock Configuration register setup(SPLLDIV2_CLK/PRESCALE = 40MHz/4 = 10MHz <=> 100ns): * Field Description * [31:24] SCKPCS 0x04 - SCK-to-PCS delay equals to (4+1 = 5)cycles of functional clock divided by TCR[PRESCALE] * [23:16] PCSSCK 0x09 - PCS-to-SCK delay equals to (9+1 = 10)cycles of functional clock divided by TCR[PRESCALE] * [15:8] DBT 0x1C - delay between transfers is (28+2 = 30)cycles of functional clock divided by TCR[PRESCALE] * [7:0] SCKDIV 0x08 - SCK period equals to (8+2 = 10)cycles of functional clock divided by TCR[PRESCALE] */ LPSPI0->CCR |= LPSPI_CCR_SCKPCS(0xFF) | LPSPI_CCR_PCSSCK(0xFF) | LPSPI_CCR_DBT(28) | LPSPI_CCR_SCKDIV(8); /* FIFO Control Register Configuration: * Field Description * [17:16] RXWATER 00b - RX Flag is set when the number of words in RX FIFO > 0 * [1:0] TXWATER 03b - TX Flag is set when the number of words in TX FIFO <= 0 */ LPSPI0->FCR |= LPSPI_FCR_RXWATER(0b00) | LPSPI_FCR_TXWATER(0b00); /* Enable LPSPI0 Module Configuration: * Field Descriptions * [9] RRF 0b - Receive FIFO not reset * [8] RTF 0b - Transmit FIFO not reset * [3] DBGEN 1b - LPSPI module is disabled in debug mode * [2] DOZEN 0b - LPSPI module is enabled in Doze mode * [1] RST 0b - Module is not reset * [0] MEN 0b - Module is disabled */ LPSPI0->CR |= LPSPI_CR_DBGEN(0b1) | LPSPI_CR_MEN(0b1); } …… /* The host shall not send any further SPI frame to NJJ29C2 * when the BUSY line is high, as it will not be stored and the data is lost. */ bool is_Busy_HighLevel( void ) { bool tmp; tmp = (bool)((PTC->PDIR >> PTC10) & 1); return tmp; } uint8_t LPSPI0_Transmit_8bits(uint8_t *send, uint8_t txLength) { uint8_t i; bool isHighLevel; /* the length should not be zero */ if (0 == txLength) { return spiCom_False; } if (true == is_Busy_HighLevel()) { do { isHighLevel = is_Busy_HighLevel(); if (timeout == is_timeout(5000)) { printf("\nCMD can not be send,because BUSY Line maintains high for 5s..."); return spiCom_False; } } while(isHighLevel == is_Busy_HighLevel()); } for(i = 0; i < txLength; i++) { /* wait for TX FIFO available */ while(!(LPSPI0->SR & LPSPI_SR_TDF_MASK)); /* transmit data */ LPSPI0->TDR = send[i]; if((i % 4) == 0) { LPSPI0_Set_TxDelay(0xC6); /* delay 20us between transfers */ } else { LPSPI0_Set_TxDelay(0x1C); /* delay 3us between transfers */ } } /* write an extra Transmit Command word to negative the SCSN */ LPSPI0->TCR = (LPSPI_TCR_CPOL(0b0) | LPSPI_TCR_CPHA(0b1) | LPSPI_TCR_PRESCALE(0b010) | LPSPI_TCR_PCS(0b00) | LPSPI_TCR_LSBF(0b0) | LPSPI_TCR_BYSW(0b0) | LPSPI_TCR_CONT(0b1) | LPSPI_TCR_CONTC(0b0) | LPSPI_TCR_RXMSK(0b0) | LPSPI_TCR_TXMSK(0b0) | LPSPI_TCR_WIDTH(0b00) | LPSPI_TCR_FRAMESZ(7));//0x53000007; return spiCom_Success; } | 
